With relocation register 14000, logical address 346 maps to:
Memory Management
Address binding, logical vs. physical addresses and the MMU, swapping, contiguous allocation (first, best and worst fit) and fragmentation, segmentation, paging and address translation, the TLB and effective access time, protection and shared pages.
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All 45 slides
- 1 Slide 1
- 2 In this lecture, we will discuss the following:
- 3 Program must be brought into memory and placed within a process
- 4 Address binding of instructions and data to memory
- 5 Slide 5
- 6 The concept of a logicaladdress space that is bound to a separate
- 7 Slide 7
- 8 MMU is a HW device that maps virtual to physical address.
- 9 A process can be swapped temporarily out of memory to a
- 10 Slide 10
- 11 ➢ If next processes to be put on CPU is not in memory, need to swap
- 12 ➢ Main memory must support both OS and user processes
- 13 Slide 13
- 14 ➢ Multiple-partition allocation
- 15 Slide 15
- 16 A variable partition memory system has the following hole sizes:
- 17 Both the first-fit and best-fit strategies for memory allocation suffer from
- 18 Solutions
- 19 Do programmers think of memory as a
- 20 Memory-management scheme that supports user view of memory.
- 21 Slide 21
- 22 Logical address consists of a two tuple:
- 23 Slide 23
- 24 Slide 24
- 25 • Consider the following segment table:
- 26 Slide 26
- 27 ➢ Paging allows the physical address space of a process to be non-
- 28 ➢ Address generated by CPU is divided into:
- 29 Slide 29
- 30 Slide 30
- 31 Slide 31
- 32 Consider a logical address space of 256 pages with a 4-KB page size, mapped onto
- 33 Consider that the physical memory is 256K, logical memory (per process) is 64K
- 34 Slide 34
- 35 Page-tablebase register ( PTBR) points to the page table.
- 36 Associative registers
- 37 Slide 37
- 38 ➢ Effective access time (EAT) is the average time needed to access
- 39 A paging scheme uses a Translation Look-aside Buffer (TLB).
- 40 A paging scheme uses a Translation Look-aside Buffer (TLB).
- 41 Memory protection in a paged environment is implemented by
- 42 Slide 42
- 43 Shared code
- 44 Slide 44
- 45 and/or segments must be loaded
Slide 1
In this lecture, we will discuss the following:
Program must be brought into memory and placed within a process
Address binding of instructions and data to memory
Slide 5
The concept of a logicaladdress space that is bound to a separate
Slide 7
MMU is a HW device that maps virtual to physical address.
Notes
MMU maps logical to physical at run time; simplest form adds the relocation (base) register.
Exam angle
A process can be swapped temporarily out of memory to a
Notes
Swapping: move a process temporarily to a backing store and back. Transfer time dominates.
Slide 10
➢ If next processes to be put on CPU is not in memory, need to swap
➢ Main memory must support both OS and user processes
Slide 13
➢ Multiple-partition allocation
Slide 15
Exam angle
Holes: 100, 500, 200, 300, 600 KB. Best fit places a 212 KB request in:
Same holes; first fit places 212 KB in:
A variable partition memory system has the following hole sizes:
Both the first-fit and best-fit strategies for memory allocation suffer from
Solutions
Notes
Trap Paging has NO external fragmentation but can have internal fragmentation in the last page.
Exam angle
Paging eliminates:
Do programmers think of memory as a
Memory-management scheme that supports user view of memory.
Slide 21
Logical address consists of a two tuple:
Slide 23
Notes
Segment table has base and limit; offset d must be < limit, else trap. Physical = base + d.
Slide 24
• Consider the following segment table:
Notes
Segment-table exercise: check d < limit first, then add base.
Exam angle
Segment 0 has base 219, limit 600. Translate (0, 430) and (0, 700).
Compare with the model answer
(0, 430): 430 < 600 → physical 219 + 430 = 649. (0, 700): 700 ≥ 600 → addressing error (trap).
Slide 26
➢ Paging allows the physical address space of a process to be non-
➢ Address generated by CPU is divided into:
Notes
Logical address = page number p (high m − n bits) + offset d (low n bits) for page size 2ⁿ and logical space 2ᵐ.
Exam angle
With 4 KB pages, how many bits are the page offset?
- 2¹² = 4096.
Slide 29
Slide 30
Slide 31
Consider a logical address space of 256 pages with a 4-KB page size, mapped onto
Notes
Exercise: logical space 256 pages × 4 KB = 2²⁰ → 20-bit logical address (8-bit page number + 12-bit offset).
Exam angle
256 pages of 4 KB each need a logical address of:
- 8 + 12.
Consider that the physical memory is 256K, logical memory (per process) is 64K
Slide 34
Page-tablebase register ( PTBR) points to the page table.
Notes
Page table in memory (PTBR, PTLR) means two memory accesses per reference; the TLB (associative cache) fixes this.
Associative registers
Slide 37
➢ Effective access time (EAT) is the average time needed to access
Exam angle
TLB 20 ns, memory 100 ns, hit ratio 80%. EAT =
- 0.8·120 + 0.2·220.
A paging scheme uses a Translation Look-aside Buffer (TLB).
A paging scheme uses a Translation Look-aside Buffer (TLB).
Memory protection in a paged environment is implemented by
Notes
Protection: a valid–invalid bit per page-table entry; also read/write/execute bits.
Slide 42
Shared code
Slide 44
and/or segments must be loaded
